This research program will develop an innovative platform for novel nanoelectronic devicescapable of replacing conventional CMOS-based technology. Using III-V semiconductor nanowires (NW) our prime goal is to realize very high-performance heterojunction tunneling fieldeffect transistors (TFET) and surround-gate FETs for future strongly scaled, energy-efficientand high-speed logic switches. Essential for this success will be a detailed understanding ofthe physical mechanisms of charge carrier transport in these 1 D-like nanostructures, as well as major improvements in material engineering and device fabrication. We will realize this by growth of advanced NW heterostructures via ultrahigh-purity methods, state-of-the-art nanofabrication into gated FET devices and characterization of the nanoscale charge carrier transportby low-noise transport measurements and ultrafast pump-probe techniques. The transportand device properties will be directly correlated with atomic-scale structural analysis viaunique atom-probe tomography metrology to establish important structure-function relationshipsrequired for advancement of device performance. This project draws upon the distinct core competences of leading groups in semiconductor NWs and their devices via a strongly multidisciplinary approach including Physics (WSI-TUM), Materials Science (NorthwesternUniversity) and Electrical Engineering (IBM Zurich).